| Focus Session: Evolution Of Ml Hardware: From Technologies To Algorithms And Architectures |
| Algorithm to Technology Co-Optimization for CiM-based Hyperdimensional Computing | |  |
| Mahta Mayahinia, Simon Thomann, Paul Genssler, Christopher Münch, Hussam Amrouch and Mehdi Tahoori |
| Accelerating Neural Networks for Large Language Models and Graph Processing with Silicon Photonics | | |
| Salma Afifi, Febin Sunny, Mahdi Nikdast and Sudeep Pasricha |
| Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads | | |
| Harsh Sharma, Gaurav Narang, Jana Doppa, Umit Y. Ogras and Partha Pratim Pande |
| ASD Technical Paper Session: Designing Adaptive Autonomous Systems for Resource-Constrained Platforms |
| Context-aware Multi-Model Object Detection for Diversely Heterogeneous Compute Systems | | |
| Justin Davis and Mehmet Belviranli |
| Adaptive localization for autonomous racing vehicles with resource-constrained embedded platforms | | |
| Federico Gavioli, Gianluca Brilli, Paolo Burgio and Davide Bertozzi |
| Adaptive Deep Learning for Efficient Visual Pose Estimation aboard Ultra-low-power Nano-drones | | |
| Beatrice Alessandra Motetti, Luca Crupi, Omer Mohammed Elamin Elshaigi Mustafa, Matteo Risso, Daniele Jahier Pagliari, Daniele Palossi and Alessio Burrello |
| BPA - Reliability And Optimizations |
| Scalable Sequential Optimization Under Observability Don't Cares | | |
| Dewmini Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli and Luca Amaru |
| VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting | | |
| Chang Meng, Hanyu Wang, Yuqi Mai, Weikang Qian and Giovanni De Micheli |
| SELCC: Enhancing MLC Reliability and Endurance with Single-cell Error Correction Codes | | |
| Yujin Lim, Dongwhee Kim and Jungrae Kim |
| FPGA Solutions |
| Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization | | |
| Jaemin Seo, Sejin Park and Seokhyeong Kang |
| An Agile Deploying Approach for Large-Scale Workloads on CGRA-CPU Architecture | | |
| Jiahang Lou, Xuchen Gao, Yiqing Mao, Yunhui Qiu, Yihan Hu, Wenbo Yin and Lingli Wang |
| Cuper: Customized Dataflow and Perceptual Decoding for Sparse Matrix-Vector Multiplication on HBM-Equipped FPGAs | | |
| Enxin Yi, Yiru Duan, Yinuo Bai, Kang Zhao, Zhou Jin and Weifeng Liu |
| Towards High-throughput Neural Network Inference with Computational BRAM on Nonvolatile FPGAs | | |
| Hao Zhang, Mengying Zhao, Huichuan Zheng, Yuqing Xiong, Yuhao Zhang and Zhaoyan Shen |
| Bitstream Fault Injection Attacks on CRYSTALS Kyber Implementations on FPGAs | | |
| Ziying Ni, ayesha khalid, Weiqiang Liu and Maire O'Neill |
| On-FPGA Spiking Neural Networks for Integrated Near-Sensor ECG Analysis | | |
| Matteo Antonio Scrugli, Paola Busia, Gianluca Leone and Paolo Meloni |
| SpecHD: Hyperdimensional Computing Framework for FPGA-based Mass Spectrometry Clustering | | |
| Sumukh Pinge, Weihong Xu, Jaeyoung Kang, Tianqi Zhang, Niema Moshiri, Wout Bittremieux and Tajana Rosing |
| Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes | | |
| Bharadwaj Madabhushi, Sandip Kundu and Daniel Holcomb |
| High-Efficiency FPGA-Based Approximate Multipliers with LUT Sharing and Carry Switching | | |
| Yi GUO, Qilin ZHOU, Xiu CHEN and Heming SUN |
| OTFGEncoder-HDC: Hardware-efficient Encoding Techniques for Hyperdimensional~Computing | | |
| Mahboobe Sadeghipourrudsari, Jonas Krautter and Mehdi Tahoori |
| Adaptive And Sensing Systems |
| OISA: Architecting an Optical In-Sensor Accelerator for Efficient Visual Computing | | |
| Mehrdad Morsali, Sepehr Tabrizchi, Deniz Najafi, Mohsen Imani, Mahdi Nikdast, Arman Roohi and Shaahin Angizi |
| PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems | | |
| Xing Huang, Jiaxuan Wang, Zhiwen Yu, Bin Guo, Tsung-Yi Ho, Ulf Schlichtmann and Krishnendu Chakrabarty |
| Multi-Agent Reinforcement Learning for Thermally-Restricted Performance Optimization on Manycores | | |
| Heba Khdr, Mustafa Enes Batur, Kanran Zhou, Mohammed Bakr Sikal and Joerg Henkel |
| OplixNet: Towards Area-Efficient Optical Split-Complex Networks with Real-to-Complex Data Assignment and Knowledge Distillation | | |
| Ruidi Qiu, Amro Eldebiky, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann and Bing Li |
| Design Automation for Organs-on-Chip | | |
| Maria Emmerich, Philipp Ebner and Robert Wille |
| Trace-enabled timing model synthesis for ROS2-based autonomous applications | | |
| Hazem Abaza, Debayan Roy, Shiqing Fan, Selma Saidi and Antonios Motakis |
| sLET for distributed aerospace landing system | | |
| Damien Chabrol, Guillaume Phavorin and Eric Jenn |
| A Mapping of Triangular Block Interleavers to DRAM for Optical Satellite Communication | | |
| Lukas Steiner, Timo Lehnigk-Emden, Markus Fehrenz and Norbert Wehn |
| OC-DLRM: Minimizing the I/O Traffic of DLRM between Main Memory and OCSSD | | |
| Shang-Hung Ti, Tseng-Yi Chen, Tsung Tai Yeh, Shuo-Han Chen and Yu-Pei Liang |
| SEAL: Sensing Efficient Active Learning on Wearables through Context-awareness | | |
| Hamidreza Alikhani Koshkak, Ziyu Wang, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani and Nikil Dutt |
| Dynamic Per-Flow Queues for TSN switches | | |
| Wenxue Wu, Zhen Li, Tong Zhang, Xiaoqin Feng, Liwei Zhang, Xuelong Qi and Fengyuan Ren |
| Microarchitectural And Side-Channel-Based Attacks And Countermeasures |
| Flush+earlyReload: Covert Channels Attack on Shared LLC Using MSHR Merging | | |
| Aditya S. Gangwar, Prathamesh N. Tanksale, Shirshendu Das and Sudeepta Mishra |
| Prime+Reset: Introducing A Novel Cross-World Covert-Channel Through Comprehensive Security Analysis on ARM TrustZone | | |
| Yun Chen, Arash Pashrashid, Yongzheng Wu and Trevor E. Carlson |
| Statistical Profiling of Micro-Architectural Traces and Machine Learning For Spectre Detection: A Systematic Evaluation | | |
| Mai AL-Zu'bi and Georg Weissenbacher |
| Three Sidekicks to Support Spectre Countermeasures | | |
| Markus Krausz, Jan Philipp Thoma, Florian Stolz, Marc Fyrbiak and Tim Güneysu |
| Detecting Backdoor Attacks in Black-Box Neural Networks through Hardware Performance Counters | | |
| Manaar Alam, Yue Wang and Michail Maniatakos |
| Can Machine Learn Pipeline Leakage? | | |
| Omid Bazangani, Parisa Amiri Eliasi, Stjepan Picek and Lejla Batina |
| A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces | | |
| Giuseppe Chiari, Davide Galli, Francesco Lattari, Matteo Matteucci and Davide Zoni |
| IMCE: An In-Memory Computing and Encrypting Hardware Architecture for Robust Edge Security | | |
| Hanyong Shao, Boyi Fu, Jinghao Yang, Wenpu Luo, Chang Su, Zhiyuan Fu, Kechao Tang and Ru Huang |
| Demonstrating Post-Quantum Remote Attestation for RISC-V Devices | | |
| Maximilian Barger, Marco Brohet and Francesco Regazzoni |
| Circumventing Restrictions in commercial High-Level Synthesis Tools | | |
| Benjamin Carrion Schaefer and Chaitali Sathe |
| IEEE Ceda Distinguished Lecturer Lunchtime Keynote |
| AI Models for Edge Computing: Hardware-aware Optimizations for Efficiency | | |
| Hai (Helen) Li |
| ASD Technical Paper Session: Towards Assuring Safe Autonomous Driving |
| Back to the Future: Reversible Runtime Neural Network Pruning for Safe Autonomous Systems | | |
| Danny Abraham, Biswadip Maity, Bryan Donyanavard and Nikil Dutt |
| Automated Traffic Scenario Description Extraction Using Video Transformers | | |
| Aron Harder and Madhur Behl |
| ADAssure: Debugging Methodology for Autonomous Driving Control Algorithms | | |
| Andrew Roberts, Mohammad Reza Heidari Iman, Mauro Bellone, Tara Ghasempouri, Olaf Maennel, Jaan Raik, Mohammad Hamad and Sebastian Steinhorst |
| BPA - New Circuits And Devices |
| Dynamic Realization of Multiple Control Toffoli Gate | | |
| Abhoy Kole, Arighna Deb, Kamalika Datta and Rolf Drechsler |
| A FeFET-based Time-Domain Associative Memory for Multi-bit Similarity Computation | | |
| Qingrong Huang, Hamza Errahmouni Barkam, Zeyu Yang, Jianyi Yang, Thomas K ̈ampfe, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Mohsen Imani, Cheng Zhuo and Xunzhao Yin |
| RVCE-FAL: A RISC-V Vector-Scalar Custom Extension for Faster FALCON Digital Signature | | |
| Xinglong Yu, Yi Sun, Yifan Zhao, Honglin Kuang and Jun Han |
| Emerging Machine Learning Techniques |
| Pipette: Automatic Fine-grained Large Language Model Training Configurator for Real-World Clusters | | |
| Jinkyu Yim, Jaeyong Song, Yerim Choi, Jaebeen Lee, Jaewon Jung, Hongsun Jang and Jinho Lee |
| A Computationally Efficient Neural Video Compression Accelerator Based on a Sparse CNN-Transformer Hybrid Network | | |
| Siyu Zhang, Wendong Mao, Huihong Shi and Zhongfeng Wang |
| MultimodalHD: Federated Learning Over Heterogeneous Sensor Modalities using Hyperdimensional Computing | | |
| Quanling Zhao, Xiaofan Yu, Shengfan Hu and Tajana Rosing |
| DyPIM: Dynamic-inference-enabled Processing-In-Memory Accelerator | | |
| Tongxin Xie, Tianchen Zhao, Zhenhua Zhu, Xuefei Ning, Bing Li, Guohao Dai, Huazhong Yang and Yu Wang |
| Multi-Level Analysis of GPU Utilization in ML Training Workloads | | |
| Paul Delestrac, Debjyoti Bhattacharjee, Simei Yang, Diksha Moolchandani, Francky Catthoor, Lionel Torres and David Novo |
| 12 mJ per Class On-Device Online Few-Shot Class-Incremental Learning | | |
| Fransiskus Yoga Esa Wibowo, Cristian Cioflan, Thorir Mar Ingolfsson, Michael Hersche, Leo Zhao, Abbas Rahimi and Luca Benini |
| Decoupled Access-Execute enabled DVFS for tinyML deployments on STM32 microcontrollers | | |
| Elisavet Lydia Alvanaki, Manolis Katsaragakis, Dimosthenis Masouros, Sotirios Xydis and Dimitrios Soudris |
| An Isotropic Shift-Pointwise Network for Crossbar-Efficient Neural Network Design | | |
| Ziyi Guan, Boyu Li, Yuan Ren, Muqun Niu, Hantao Huang, Graziano Chesi, Hao Yu and Ngai Wong |
| MicroNAS: Zero-Shot Neural Architecture Search for MCUs | | |
| Ye Qiao, Haocheng Xu, Yifan Zhang and Sitao Huang |
| Zero-shot Classification using Hyperdimensional Computing | | |
| Samuele Ruffino, Geethan Karunaratne, Michael Hersche, Luca Benini, Abu Sebastian and Abbas Rahimi |
| Accelerating DNNs using Weight Clustering on RISC-V Custom Functional Units | | |
| Muhammad Sabih, Batuhan Sesli, Frank Hannig and Jürgen Teich |
| ASD Technical Paper Session: On Perception in Autonomous Systems |
| Adaptive Perception Control for Aerial Robots with Twin Delayed DDPG | | |
| Marilyn Wolf |
| Frontiers in Edge AI with RISC-V: Hyperdimensional Computing vs. Quantized Neural Networks | | |
| Hussam Amrouch, Paul Genssler, Sandy A. Wasif, Miran Wael and Rodion Novkin |
| Driving Autonomy with Event-based Cameras: Algorithm and Hardware Perspectives | | |
| Saibal Mukhopadhyay |
| Corporate Governance and Management of AI-Driven Product Development: Vehicle Automation | | |
| Marilyn Wolf |
| Focus Session: Formal Verification Under Resource Constraints |
| Polynomial Formal Verification of Sequential Circuits | | |
| Caroline Dominik and Rolf Drechsler |
| Automated Verifiability-Driven Design of Approximate Circuits: Exploiting Error Analysis | | |
| Zdenek Vasicek, Vojtech Mrazek and Lukas Sekanina |
| Using Formal Verification Methods for Optimization of Circuits under External Constraints | | |
| Daniel Grosse, Lucas Klemmer and Dominik Bonora |
| Combining Formal Verification and Testing for Debugging of Arithmetic Circuits | | |
| Jiteshri Dasari and Maciej Ciesielski |
| BPA - Novel Architecture Solutions |
| FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural Networks | | |
| Xueyuan Liu, Zhuoran Song, Guohao Dai, Gang Li, Can Xiao, Yan Xiang, Dehui Kong, Ke Xu and Xiaoyao Liang |
| Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph Isomorphism | | |
| Yifeng Xiao, Chanwook Oh, Michele Lora and Pierluigi Nuzzo |
| Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors | | |
| Gideon Mohr, Marco Guarnieri and Jan Reineke |
| System-Level Design Methodologies And High-Level Synthesis |
| PIMLC: Logic Compiler for Bit-serial Based PIM | | |
| Chenyu Tang, Chen Nie, Weikang Qian and Zhezhi He |
| PIMSYN: Synthesizing Processing-in-memory CNN Accelerators | | |
| Wanqian Li, Xiaotian Sun, Xinyu Wang, Lei Wang, Yinhe Han and Xiaoming Chen |
| MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications | | |
| Tousif Rahman, Gang Mao, Sidharth Maheshwari, Rishad Shafik and Alex Yakovlev |
| Subgraph Extraction-based Feedback-guided Iterative Scheduling for HLS | | |
| Hanchen Ye, David Z. Pan, Chris Leary, Deming Chen and Xiaoqing Xu |
| Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs | | |
| Mingzhe Gao, Jieru Zhao, Zhe Lin and Minyi Guo |
| CASCO: Cascaded Co-Optimization for Holistic Neural Network Acceleration | | |
| Bahador Rashidi, Shan Lu, kiarash aghakasiri, Chao Gao, Fred Xuefei Han, Zhisheng Wang, Laiyuan Gong and Fengyu Sun |
| BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0 | | |
| Emad Arasteh, Vivek Govindasamy and Rainer Doemer |
| SenseDSE: Sensitivity-based Performance Evaluation for Design Space Exploration of Microarchitecture | | |
| Zheng Wu, Xiaoling Yi, Li Shang and Fan Yang |
| Microprocessor Design Space Exploration via Space Partitioning and Bayesian Optimization | | |
| Zijun JIANG and Yangdi Lyu |
| DeepSeq: Deep Sequential Circuit Learning | | |
| Sadaf Khan, Zhengyuan Shi, Min Li and Qiang Xu |
| Emerging Design Technologies For Future Computing |
| Para-ZNS: Improving Small-zone ZNS SSDs Parallelism through Dynamic Zone Mapping | | |
| Zhenhua Tan, Linbo Long, Jingcheng Shen, Congming Gao, Renping Liu and Yi Jiang |
| Quantum State Preparation Using an Exact CNOT Synthesis Formulation | | |
| Hanyu Wang, Jason Cong and Giovanni De Micheli |
| BlockAMC: Scalable In-Memory Analog Matrix Computing for Solving Linear Systems | | |
| Lunshuai Pan, Pushen Zuo, Yubiao Luo, Zhong Sun and Ru Huang |
| A Parallel Tempering Processing Architecture with Multi-Spin Update for Fully-Connected Ising Models | | |
| Yang Zhang, Xiangrui Wang, Dong Jiang, Zhanhong Huang, Gaopeng Fan and Enyi Yao |
| A3PIM: An Automated, Analytic and Accurate Processing-in-Memory Offloader | | |
| Qingcai Jiang, Shaojie Tan, Junshi Chen and Hong An |
| HygHD: Hyperdimensional Hypergraph Learning | | |
| Jaeyoung Kang, You Hak Lee, Minxuan Zhou, Weihong Xu and Tajana Rosing |
| SuperFlow: A Fully-Customized RTL-to-GDS Design Automation Flow for Adiabatic Quantum-Flux-Parametron Superconducting Circuits | | |
| Yanyue Xie, Peiyan Dong, Geng Yuan, Zhengang Li, Masoud Zabihi, Chao Wu, Sung-En Chang, Xufeng Zhang, Xue Lin, Caiwen Ding, Nobuyuki Yoshikawa, Olivia Chen and Yanzhi Wang |
| JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits | | |
| Siyan Chen, Rongliang Fu, Junying Huang, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho and Dongrui Fan |
| AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator using Adaptive Posit | | |
| Jingyu He, Fengbin Tu, Tim Cheng and Chi Ying Tsui |
| DNA-based Similar Image Retrieval via Triplet Network-driven Encoder | | |
| Takefumi Koike, Hiromitsu Awano and Takashi Sato |
| Unleashing the Power of T1-cells in SFQ Arithmetic Circuits | | |
| Rassul Bairamkulov, Mingfei Yu and Giovanni De Micheli |
| Focus Session: Cryogenic Computing: Current Status And Future Perspectives |
| Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization | | |
| Daniel Bochen Tan, Shuohao Ping and Jason Cong |
| From Master equation to SPICE: a platform to model cryo-CMOS control for qubits | | |
| Vladimir Pesic, Andrew Wright and Edoardo Charbon |
| Technology-Aware Logic Synthesis for Superconducting Electronics | | |
| Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Marakkalage, Mingfei Yu and Giovanni De Micheli |
| Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic | | |
| Sasan Razmkhah, Robert Aviles, Mingye li, Sandeep Gupta, Peter Beerel and Massoud Pedram |
| ASD Technical Paper Session: Real-Time Aware Communication Systems for Autonomy |
| An Adaptive UAV Scheduling Process to Address Dynamic Mobile Network Demand Efficiently | | |
| Ruide Cao, Jiao Ye, Jin Zhang, Qian You, Chao Tang, Yan Liu and Yi Wang |
| End-to-End Latency Optimization of Thread Chains Under the DDS Publish/Subscribe Middleware | | |
| Gerlando Sciangula, Daniel Casini, Alessandro Biondi and Claudio Scordino |
| Orchestration-aware optimization of ROS2 communication protocols | | |
| Mirco De Marchi and Nicola Bombieri |
| BPA - Better Machine Learning |
| Class-Aware Pruning for Efficient Neural Networks | | |
| Mengnan Jiang, Jingcun Wang, Amro Eldebiky, Xunzhao Yin, Cheng Zhuo, Ing-Chao Lin and Grace Li Zhang |
| Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations | | |
| Soyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel and Mehdi Tahoori |
| HW-SW Optimization of DNNs for Privacy-preserving People Counting on Low-resolution Infrared Arrays | | |
| Matteo Risso, Chen Xie, Francesco Daghero, Alessio Burrello, Seyedmorteza Mollaei, Marco Castellano, Enrico Macii, Massimo Poncino and Daniele Jahier Pagliari |
| System Simulation, Validation And Verification |
| EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves | | |
| Aruna Jayasena, Richard Bachmann and Prabhat Mishra |
| Heterogeneous Static Timing Analysis with Advanced Delay Calculator | | |
| Zizheng Guo, Tsung-Wei Huang, Jin Zhou, Cheng Zhuo, Yibo Lin, Runsheng Wang and Ru Huang |
| TSA-TICER: A Two-Stage TICER Acceleration Framework for Model Order Reduction | | |
| Pengju Chen, Dan Niu, Zhou Jin, Changyin Sun, Qi Li and Hao Yan |
| A RISC-V "V" VP: Unlocking Vector Processing for Evaluation at the System Level | | |
| Manfred Schlaegl, Moritz Stockinger and Daniel Grosse |
| ARTmine: Automatic Association Rule Mining with Temporal Behavior for Hardware Verification | | |
| Mohammad Reza Heidari Iman, Gert Jervan and Tara Ghasempouri |
| MSH: A Multi-Stage HiZ-Aware Homotopy Framework for Nonlinear DC Analysis | | |
| Zhou Jin, Tian Feng, Xiao Wu, Dan Niu, Zhenya Zhou and Cheng Zhuo |
| Selfie5: an autonomous, self-contained verification approach for high-throughput random testing of programmable processors. | | |
| Yehuda Kra, Naama Kra and Adam Teman |
| ISPT-Net: A Noval Transient Backward-stepping Reduction Policy by Irregular Sequential Prediction Transformer | | |
| Yichao Dong, Dan Niu, Zhou Jin, Chuan Zhang, Changyin Sun and Zhenya Zhou |
| VeriBug: An Attention-based Framework for Bug Localization in Hardware Designs | | |
| Giuseppe Stracquadanio, Sourav Medya, Stefano Quer and Debjit Pal |
| An Endeavor to Industrialize Hardware Fuzzing: Automating NoC Verification in UVM | | |
| Ruiyang Ma, Huatao Zhao, Jiayi Huang, Shijian Zhang and Guojie Luo |
| Modeling And Mitigation Of Defects, Faults, Variability, And Reliability |
| LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND Flash | | |
| Shuhan BAI, You ZHOU, Fei WU, Changsheng XIE, Tei-Wei KUO and Chun Jason XUE |
| Learning Assisted Post-Manufacture Testing and Tuning of RRAM-Based DNNs for Yield Recovery | | |
| Kwondo Ma, Anurup Saha, Chandramouli Amarnath and Abhijit Chatterjee |
| A Graph-learning-driven Prediction Method for Combined Electromigration and Thermomigration Stress on Multi-Segment Interconnects | | |
| Yunfan Zuo, Yuyang Ye, Hongchao Zhang, Tinghuan Chen, Hao Yan and Longxing Shi |
| PoLM: Point Cloud and Large Pre-trained Model Catch Mixed-type Wafer Defect Pattern Recognition | | |
| Hongquan He, Guowen Kuang, QI SUN and Hao Geng |
| Derailed: Arbitrarily Controlling DNN Outputs with Targeted Fault Injection Attacks | | |
| Jhon Ordoñez and Chengmo Yang |
| IoT-GRAF: IoT Graph Learning-based Anomaly and Intrusion Detection through Multi-modal Data Fusion | | |
| Rozhin Yasaei, Yasamin Moghaddas and Mohammad Al Faruque |
| Alleviating Barren Plateaus in Parameterized Quantum Machine Learning Circuits: Investigating Advanced Parameter Initialization Strategies | | |
| Muhammad Kashif, Muhammad Rashid, Saif Al-Kuwari and Muhammad Shafique |
| FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators | | |
| Pratyush Dhingra, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Jana Doppa, Ananth Kalyanaraman and Partha Pratim Pande |
| Towards SEU Fault Propagation Prediction with Spatio-temporal Graph Convolutional Networks | | |
| Li Lu, Junchao Chen, Markus Ulbricht and Milos Krstic |
| Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model | | |
| Jingyu Jia, Jianwang Zhai and Kang Zhao |
| Out-of-Distribution Detection Using Power-Side Channels for Improving Functional Safety of Neural Network FPGA Accelerators | | |
| Vincent Meyers, Dennis Gnad and Mehdi Tahoori |
| Multi-Partner Projects |
| EMDRIVE Architecture: Embedded Computing and Diagnostics from Sensor to Edge | | |
| Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Juergen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan and Albrecht Mayer |
| Evaluating an open-source hardware approach from HDL to GDS for a security chip design — a review of the final stage of project HEP | | |
| Norbert Herfurth, Tim Henkes, Tuba Kiyan, Fabian Buschkowski, Christoph Lüth, Steffen Reith, Pascal Sasdrich, Milan Funk, Rene Rathfelder, Aygün Walter, Julian Wälde, Goran Panic, Levente Suta, Detlef Boeck, Arnd Weber and Torsten Grawunder |
| The 3D Neural Network Compute Cube (N2C2) Concept enabling Efficient Hardware Transformer Architectures towards Speech-to-Speech Translation | | |
| Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cedric Marchand, Jens Trommer, Cigdem Cakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Muller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordea, Charles Brazier, Yifan Wang, Chhandak Mukherjee, Marina Deng, Marc François, Houssem Rezgui, Reveil Lucas and Cristell Maneux |
| A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing | | |
| Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner and Wolfgang Ecker |
| NeuSpin: Design of A Reliable Edge Neuromorphic System Based On Spintronics for Green AI | | |
| Soyed Tuhin Ahmed, Kamal Danouchi, Guillaume Prenat, Lorena Anghel and Mehdi Tahoori |
| Autonomous Realization of Safety- and Time-Critical Embedded Artificial Intelligence | | |
| Joakim Lindén, Andreas Ermedahl, Hans Salomonsson, Masoud Daneshtalab, Björn Forsberg and Paris Carbone |
| ASD Embedded Keynote |
| Certainty or Intelligence: Pick One! | | |
| Edward Lee |
| ASD Posters |
| Constraint-aware Resource Management for Cyber-Physical Systems | | |
| Justin McGowen, Ismet Dagli, Neil Dantam and Mehmet Belviranli |
| Robustness and Accuracy Evaluations of Localization Techniques for Autonomous Racing | | |
| Tian Yi Lim, Nicolas Baumann, Edoardo Ghignone and Michele Magno |
| A Stakeholder Analysis on Operational Design Domains of Automated Driving Systems | | |
| Marcel Aguirre Mehlhorn, Hauke Dierend, Andreas Richter and Yuri Shardt |
| Emerging Design Technologies For Future Memories |
| COMET: A Cross-Layer Optimized Optical Phase Change Main Memory Architecture | | |
| Febin Sunny, Amin Shafiee, Benoit Charbonnier, Mahdi Nikdast and Sudeep Pasricha |
| CafeHD: A Charge-Domain FeFET-Based Compute-in-Memory Hyperdimensional Encoder with Hypervector Merging | | |
| Taixin Li, Hongtao Zhong, Juejian Wu, Thomas Kämpfe, Kai Ni, Vijaykrishnan Narayanan, Huazhong Yang and Xueqing Li |
| AFPR-CIM: An Analog-Domain Floating-Point RRAM-based Compute-In-Memory Architecture with Dynamic Range Adaptive FP-ADC | | |
| Haobo Liu, Zhengyang Qian, Wei Wu, Hongwei Ren, Zhiwei Liu and Leibin Ni |
| ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test | | |
| Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng and Chixiao Chen |
| Bit-Trimmer: Ineffectual Bit-operation Removal for CIM Architecture | | |
| Yintao He, Shixin Zhao, Songyun Qu, Huawei Li, Xiaowei Li and Ying Wang |
| HyQA: Hybrid Near-Data Processing Platform for Embedding based Question Answering System | | |
| Shengwen Liang, Ziming Yuan, Ying Wang, Dawen Xu, Huawei Li and Xiaowei Li |
| Towards Efficient Reconfiguration through Lightweight Input Inversion for MLC NVFPGAs | | |
| Huichuan Zheng, Mengying Zhao, Hao Zhang, Yuqing Xiong, Xiaojun Cai and Zhiping Jia |
| Low Power and Temperature-Resilient Compute-In-Memory Based on Subthreshold-FeFET | | |
| Yifei Zhou, Xuchu Huang, Jianyi Yang, Kai Ni, Hussam Amrouch, Cheng Zhuo and Xunzhao Yin |
| Pipeline Design of Nonvolatile-based Computing in Memory for Convolutional Neural Networks Inference Accelerators | | |
| Lixia Han, Peng Huang, Zheng Zhou, Yiyang Chen, Haozhang Yang, Xiaoyan Liu and Jinfeng Kang |
| ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis | | |
| Tsung-Yu Liu, Yen An Lu, James Yu, Chin-Fu Nien and Hsiang-Yun Cheng |
| A DTCO Framework for 3D NAND Flash Readout | | |
| Mattia Gerardi, Arvind Sharma, Yang Xiang, Jakub Kaczmarek, Fernando Garcia Redondo, Maarten Rosmeulen and Marie Garcia Bardon |
| Efficient And Secure Systems-On-Chip For The New Hyperconnected Environments |
| Efficient Fast Additive Homomorphic Encryption Cryptoprocessor for Privacy-preserving Federated Learning Aggregation | | |
| Wenye Liu, Nazim Altar Koca and Chip Hong Chang |
| CALLOC: Curriculum Adversarial Learning for Secure and Robust Indoor Localization | | |
| Danish Gufran and Sudeep Pasricha |
| Optimizing Ciphertext Management for Faster Fully Homomorphic Encryption Computation | | |
| Eduardo Chielle, Oleg Mazonka and Michail Maniatakos |
| Cache Bandwidth Contention Leaks Secrets | | |
| Han Wang, Ming Tang, Ke Xu and Quancheng Wang |
| IOMMU Deferred Invalidation Vulnerability: Exploit and Defense | | |
| Chathura Rajapaksha, Leila Delshadtehrani, Richard Muri, Manuel Egele and Ajay Joshi |
| EMAClave: An Efficient Memory Authentication for RISCV Enclaves | | |
| Omais Pandith, Rafail Psiakis and Johanna Toivanen |
| ROLDEF: RObust Layered DEFense for Intrusion Detection Against Adversarial Attacks | | |
| Onat Gungor, Tajana Rosing and Baris Aksanli |
| Beyond Random Inputs: A Novel ML-Based Hardware Fuzzing | | |
| Mohamadreza Rostami, Marco Chilese, Shaza Zeitouni, Rahul Kande, Jeyavijayan Rajendran and Ahmad-Reza Sadeghi |
| HDCircuit: Brain-inspired Hyperdimensional Computing for Circuit Recognition | | |
| Paul Genssler, Lilas Alrahis, Ozgur Sinanoglu and Hussam Amrouch |
| Securing ISW Masking Scheme Against Glitches | | |
| Sofiane Takarabt, Mohammad Ebrahimabadi, Javad Bahrami, Sylvain Guilley and Naghmeh Karimi |
| Efficient Optimization Techniques For Machine Learning Architectures |
| BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network | | |
| Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng and An-Yeu Andy Wu |
| Communication-Efficient Model Parallelism for Distributed In-Situ Transformer Inference | | |
| Yuanxin Wei, Shengyuan Ye, Jiazhi Jiang, Xu Chen, Dan Huang, Jiangsu Du and Yutong Lu |
| DIAPASON: Differentiable Allocation, Partitioning and Fusion of Neural Networks for Distributed Inference | | |
| Federico Peccia, Alexander Viehl and Oliver Bringmann |
| DiMO-Sparse: Differentiable Modeling and Optimization of Sparse CNN Dataflow and Hardware Architecture | | |
| Jianfeng Song, Rongjian Liang, Yu Gong, Bo Yuan and Jiang Hu |
| GPACE: An Energy-Efficient PQ-based GCN Accelerator with Redundancy Reduction | | |
| Yibo Du, Shengwen Liang, Ying Wang, Huawei Li, Xiaowei Li and yinhe han |
| Automated Optimization of Deep Neural Networks: Dynamic Bit-Width and Layer-Width Selection via Cluster-Based Parzen Estimation | | |
| Seyedarmin Azizi, Mahdi Nazemi, Arash Fayyazi and Massoud Pedram |
| ViT-ToGo : Vision Transformer Accelerator with Grouped Token Pruning | | |
| Seungju Lee, Kyumin Cho, Eunji Kwon, Sejin Park, Seojeong Kim and Seokhyeong Kang |
| SEA: Sign-Separated Accumulation Scheme for Resource-Efficient DNN Accelerators | | |
| Jing Gong, Hassaan Saadat, Haris Javaid, Hasindu Gamaarachchi, David Taubman and Sri Parameswaran |
| Towards Forward-Only Learning for Hyperdimensional Computing | | |
| Hyunsei Lee, Hyukjun Kwon, Jiseung Kim, Seohyun Kim, Mohsen Imani and Yeseong Kim |
| Special Day on Sustainable Computing Lunchtime Keynote |
| Data Center Demand Response for Sustainable Computing: Myth or Opportunity? | | |
| Ayse Coskun |
| Architecture And Interconnect Design |
| NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator | | |
| Mohit Upadhyay, Rohan Juneja, Weng-Fai Wong and Li-Shiuan Peh |
| IndexMAC: A Custom RISC-V Vector Instruction to Accelerate Structured-Sparse Matrix Multiplications | | |
| Vasileios Titopoulos, Kosmas Alexandridis, Christodoulos Peltekis, Chrysostomos Nicopoulos and Giorgos Dimitrakopoulos |
| LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation | | |
| Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler and Luca Benini |
| MACO: Exploring GEMM Acceleration on a Loosely-Coupled Multi-core Processor | | |
| Bingcai Sui, Junzhong Shen, Caixia Sun, Junhui Wang, Zhong Zheng and Wei Guo |
| DRAM-Locker: A General-Purpose DRAM Protection Mechanism against Adversarial DNN Weight Attacks | | |
| Ranyang Zhou, Sabbir Ahmed, Arman Roohi, Adnan Siraj Rakin and Shaahin Angizi |
| Towards Scalable GPU System with Silicon Photonic Chiplet | | |
| Chengeng Li, Fan Jiang, Shixi Chen, Xianbin LI, Jiaqi Liu, Wei Zhang and Jiang Xu |
| Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV | | |
| Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti and Luca Benini |
| STAR: Sum-Together/Apart Reconfigurable Multipliers for Precision-Scalable ML Workloads | | |
| Edward Manca, Luca Urbinati and Mario R. Casu |
| Harnessing ML Privacy by Design Through Crossbar Array Non-idealities | | |
| Md Shohidul Islam, Sankha B Dutta, Andres Marquez, Ihsen Alouani and Khaled Khasawneh |
| Approximate And Efficient Computing |
| PACE: A Piece-Wise Approximate and Configurable Floating-Point Divider for Energy-Efficient Computing | | |
| Chenyi Wen, Haonan Du, Zhengrui Chen, Li Zhang, QI SUN and Cheng Zhuo |
| AttBind: Memory-efficient Acceleration for Long-range Attention using Vector-derived Symbolic Binding | | |
| Weihong Xu, Jaeyoung Kang and Tajana Rosing |
| A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training | | |
| Sami BEN ALI, Olivier Sentieys and Silviu-Ioan Filip |
| DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference | | |
| Lorenzo Sonnino, Shaswot Shresthamali, Yuan He and Masaaki Kondo |
| Embedding Hardware Approximations in Discrete Genetic-based Training for Printed MLPs | | |
| Florentia Afentaki, Michael Hefenbrock, Georgios Zervakis and Mehdi Tahoori |
| A configurable approximate multiplier for CNNs using partial product speculation | | |
| Xiaolu Hu, Ao Liu, Xinkuang Geng, Zizhong Wei, Kai Jiang and Honglan Jiang |
| ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer | | |
| Tong Xie, Yixuan Hu, Renjie Wei, Meng Li, Yuan Wang, Runsheng Wang and Ru Huang |
| A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration | | |
| Ya Wang, Hanwei FAN, Sicheng Li, Tingyuan Liang and Wei ZHANG |
| CLAST: Cross-Layer Approximate High-Level Synthesis with Configurable Approximate Three-Operand Adders | | |
| Jian Shi, Wenjing Zhang and Weikang Qian |
| Embedded Software And Tool Chains |
| ECM: Improving IoT Throughput with Energy-Aware Connection Management | | |
| Fatemeh Ghasemi, Lukas Liedtke and Magnus Jahre |
| Full-Stack Optimization for CAM-Only DNN Inference | | |
| Joao Paulo De Lima, Asif Ali Khan, Luigi Carro and Jeronimo Castrillon |
| Discovering Efficient Fused Layer Configurations for Executing Multi-Workloads on Multi-core NPUs | | |
| Younghyun Lee, Hyejun Kim, Yongseung Yu, Myeongjin Cho, Jiwon Seo and Yongjun Park |
| CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures | | |
| Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers and Jan Moritz Joseph |
| High Throughput Hardware Accelerated CoreSight Trace Decoding | | |
| Matthew Edwin Weingarten, Nora Hossle and Timothy Roscoe |
| Computational and Storage Efficient Quadratic Neurons for Deep Neural Networks | | |
| Chuangtao Chen, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann and Bing Li |
| Performance Analysis and Optimizations of Matrix Multiplications on ARMv8 Processors | | |
| Hucheng Liu, Shaohuai Shi, Xuan Wang, Zoe L. Jiang and Qian Chen |
| A Compiler Phase to Optimally Split GPU Wavefronts for Safety-Critical Systems | | |
| Artem Klashtorny, Mahesh Tripunitara and Hiren Patel |
| Lightweight Instrumentation for Accurate Performance Monitoring in RTOSes | | |
| Bruno Endres Forlin, Kuan-Hsun Chen, Nikolaos Alachiotis, Luca Cassano and Marco Ottavi |
| Focus Session: Resilient Cognitive Sensing And Inference In Distributed And Dynamic Environments |
| HaLo-FL: Hardware-Aware Low-Precision Federated Learning | | |
| Yeshwanth Venkatesha, Abhiroop Bhattacharjee, Abhishek Moitra and Priyadarshini Panda |
| Cognitive Sensing for Energy-efficient Edge Intelligence | | |
| Minah Lee, Sudarshan Sharma, Wei Chun Wang, Hemant Kumawat, Nael Mizanur Rahman and Saibal Mukhopadhyay |
| Unearthing the Potential of Spiking Neural Networks | | |
| Sayeed Shafayet Chowdhury, Adarsh Kosta, Deepika Sharma, Marco Apolinario and Kaushik Roy |
| Navigating the Unknown: Uncertainty-Aware Compute-in-Memory Autonomy of Edge Robotics | | |
| Nastaran Darabi, Priyesh Shukla, Dinithi Jayasuriya, Divake Kumar, Alex Stutts and Amit Trivedi |
| Architectural And Microarchitectural Design Solutions |
| ViTA: A Highly Efficient Dataflow and Architecture for Vision Transformers | | |
| Chunyun Chen, Lantian Li and Mohamed M. Sabry Aly |
| Sava: A Spatial- and Value-Aware Accelerator for Point Cloud Transformer | | |
| Xueyuan Liu, Zhuoran Song, Xiang Liao, Xing Li, Tao Yang, Fangxin Liu and Xiaoyao Liang |
| Efficient Design of a Hyperdimensional Processing Unit for Multi-Layer Cognition | | |
| Mohamed Ibrahim, Youbin Kim and Jan Rabaey |
| EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-processing | | |
| Yuya Isaka, Nau Sakaguchi, Michiko Inoue and Michihiro Shintani |
| Accelerating Chaining in Genomic Analysis Using RISC-V Custom Instructions | | |
| Kisaru Liyanage, Hasindu Gamaarachchi, Hassaan Saadat, Tuo Li, Hiruna Samarakoon and Sri Parameswaran |
| ONE SA: Enabling Nonlinear Operations in Systolic Arrays For Efficient and Flexible Neural Network Inference | | |
| Ruiqi Sun, Yinchen Ni, Jie Zhao, Xin He and An Zou |
| DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators | | |
| Tom Glint, Mithil Pechimuthu and Joycee Mekie |
| S-LGCN: Software-hardware co-design for accelerating LightGCN | | |
| Shun Li, Ruiqi Chen, Enhao Tang, Jing Yang, Yajing Liu and Kun Wang |
| FLInt: Exploiting Floating Point Enabled Integer Arithmetic for Efficient Random Forest Inference | | |
| Christian Hakert, Kuan-Hsun Chen and Jian-Jia Chen |
| I²SR: Immediate Interrupt Service Routine on RISC-V MCU to Control mmWave RF Transceivers | | |
| Jimin Lee, Sangwoo Park, Junho Huh, Sanghyo Jeong, Inhwan Kim and Jae Min Kim |
| Verified Real-Time Systems |
| Fault-Tolerant Cyclic Queuing and Forwarding in Time-Sensitive Networking | | |
| Liwei Zhang, Tong Zhang, Wenxue Wu, Xiaoqin Feng, Guoxi Lin and Fengyuan Ren |
| Hardware-Assisted Control-Flow Integrity Enhancement for IoT Devices | | |
| Weiyi Wang, Lang Feng, Zhiguo Shi, Cheng Zhuo and Jiming Chen |
| PP-HDC: A Privacy-Preserving Inference Framework For Hyperdimensional Computing | | |
| Ruixuan Wang, Wengying Wen, Kyle Juretus and Xun Jiao |
| Shared Cache Analysis under Preemptive Scheduling | | |
| Thilo Fischer and Heiko Falk |
| Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? | | |
| Safin Bayes, Mohamed Hossam and Mohamed Hassan |
| Optimal Fixed Priority Scheduling in Multi-Stage Multi-Resource Distributed Real-Time Systems | | |
| Niraj Kumar, Chuanchao Gao and Arvind Easwaran |
| Real-Time Multi-Person Identification and Tracking via HPE and IMU Data Fusion | | |
| Nicola Bombieri, Mirco De Marchi, Graziano Pravadelli and Cristian Turetta |
| AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs | | |
| Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi and Luca Benini |
| SGPRS: Seamless GPU Partitioning Real-Time Scheduler for Periodic Deep Learning Workloads | | |
| Amir Fakhim Babaei and Thidapat (Tam) Chantem |
| Lightweight and predictable memory virtualization on medium-size microcontrollers | | |
| Stefano Mercogliano, Daniele Ottaviano, Alessandro Cilardo and Marcello Cinque |
| Motivating the Use of Machine-Learning For Improving Timing Behaviour of Embedded Mixed-Criticality Systems | | |
| Vikash Kumar, Behnaz Ranjbar and Akash Kumar |
| Integrity And Ip Protection For Security-Critical Circuits |
| Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning | | |
| Rahul Vishwakarma and Amin Rezaei |
| Programmable EM Sensor Array for Golden-Model Free Run-time Trojan Detection and Localization | | |
| Hanqiu Wang, Max Panoff, Zihao Zhan, Shuo Wang, Christophe Bobda and Domenic Forte |
| KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking | | |
| Levent Aksoy, Muhammad Yasin and Samuel Pagliarini |
| TroScan: Enhancing On-Chip Delivery Resilience to Physical Attack through Frequency-Triggered Key Generation | | |
| Jianfeng Wang, Shuwen Deng, Huazhong Yang, Vijaykrishnan Narayanan and Xueqing Li |
| A Golden-Free Formal Method for Trojan Detection in Non-Interfering Accelerators | | |
| Anna Lena Duque Antón, Johannes Müller, Lucas Deutschmann, Mohammad Rahmani Fadiheh, Dominik Stoffel and Wolfgang Kunz |
| TitanCFI: Toward Enforcing Control-Flow Integrity in the Root-of-Trust | | |
| Emanuele Parisi, Alberto Musa, Simone Manoni, Maicol Ciani, Davide Rossi, Francesco Barchi, Andrea Bartolini and Andrea Acquaviva |
| RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation | | |
| Nurun Mondol, Arash Vafaei, Kimia Zamiri Azar, Farimah Farahmandi and Mark Tehranipoor |
| A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing | | |
| Jiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu and Shahar Kvatinsky |
| Automated Hardware Security Countermeasure Integration inside High-Level Synthesis | | |
| Amalia Koufopoulou, Athanasios Papadimitriou, Mihalis Psarakis and David Hély |
| ScanCamouflage: Obfuscating Scan Chains with Camouflaged Sequential and Logic Gates | | |
| Tarik Ibrahimpasic, Grace Li Zhang, Michaela Brunner, Georg Sigl, Bing Li and Ulf Schlichtmann |
| Low-Power And Energy-Efficient Design |
| Algorithm-hardware co-design for Energy-Efficient A/D conversion in ReRAM-based accelerators | | |
| Chenguang Zhang, Zhihang Yuan, Xingchen Li and Guangyu Sun |
| An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint | | |
| Lingfeng Zhou, Shanlin Xiao, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang and Zhiyi Yu |
| PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors | | |
| Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann and Luca Benini |
| Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics | | |
| Donger Luo, QI SUN, Qi Xu, Tinghuan Chen and Hao Geng |
| Parallel Multi-objective Bayesian Optimization Framework for CGRA Microarchitecture | | |
| Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu, Song Chen and Yi Kang |
| Efficient Spectral-Aware Power Supply Noisy Analysis for Low-Power Design Verification | | |
| Yinuo Bai, Xiaoyu Yang, Yicheng Lu, Dan Niu, Cheng Zhuo, Zhou Jin and Weifeng Liu |
| Compact Powers-of-Two: An Efficient Non-Uniform Quantization for Deep Neural Networks | | |
| Xinkuang Geng, Siting Liu, Jianfei Jiang, Kai Jiang and Honglan Jiang |
| TreeRNG: Binary Tree Gaussian Random Number Generator for Efficient Probabilistic AI Hardware Design | | |
| Jonas Crols, Guilherme Paim, Shirui Zhao and Marian Verhelst |
| DACO: Pursuing Ultra-low Power Consumption via DNN-Adaptive CPU-GPU CO-optimization on Mobile Devices | | |
| Yushu Wu, Chao Wu, Geng Yuan, Yanyu Li, Weichao Guo, Jing Rao, Xipeng Shen, Bin Ren and Yanzhi Wang |
| LESS: Low-power Energy-efficient Subgraph Isomorphism on FPGA | | |
| Roberto Bosio, Giovanni Brignone, Filippo Minnella, Muhammad Usman Jamal and Luciano Lavagno |
| Applications Of Emerging Technologies |
| High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics | | |
| Taha Shahroodi, Raphael Cardoso, Alberto Bosio, Stephan Wong, Ian O'Connor and Said Hamdioui |
| uHD: Unary Processing for Lightweight and Dynamic Hyperdimensional Computing | | |
| Sercan Aygun, Mehran Shoushtari Moghadam and M. Hassan Najafi |
| Towards Reliable and Energy-Efficient RRAM based Discrete Fourier Transform Accelerator | | |
| Jianan Wen, Andrea Baroni, Eduardo Perez, Max Uhlmann, Markus Fritscher, Karthik KrishneGowda, Markus Ulbricht, Christian Wenger and Milos Krstic |
| Dynamic Reconfigurable Security Cells based on Emerging Devices Integrable in FDSOI Technology | | |
| Niladri Bhattacharjee, Viktor Havel, Nima Kavand, Jorge Navarro Quijada, Akash Kumar, Thomas Mikolajick and Jens Trommer |
| Analog Printed Spiking Neuromorphic Circuit | | |
| Priyanjana Pal, Haibin Zhao, Maha Shatta, Michael Hefenbrock, Sina Bakhtavari Mamaghani, Sani Nassif, Michael Beigl and Mehdi Tahoori |
| TT-SNN: Tensor Train Decomposition for Efficient Spiking Neural Network Training | | |
| Donghyun Lee, Ruokai Yin, Youngeun Kim, Abhishek Moitra, Yuhang Li and Priyadarshini Panda |
| SCGen: A Versatile Generator Framework for Agile Design of Stochastic Circuits | | |
| Zexi Li, Haoran Jin, Kuncai Zhong, Guojie Luo, Runsheng Wang and Weikang Qian |
| Approximation Algorithm for Noisy Quantum Circuit Simulation | | |
| Mingyu Huang, Ji Guan, Wang Fang and Mingsheng Ying |
| RTSA: An RRAM-TCAM based In-Memory-Search Accelerator for Sub-100 μs Collision Detection | | |
| Jiahao Sun, Fangxin Liu, Yijian Zhang, Li Jiang and Rui Yang |
| Towards Cycle-based Shuttling for Trapped-Ion Quantum Computers | | |
| Daniel Schoenberger, Stefan Hillmich, Matthias Brandl and Robert Wille |
| Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2x1 Surface | | |
| Marcel Walter, Jeremiah Croshaw, Samuel Sze Hang Ng, Konrad Walus, Robert Wolkow and Robert Wille |
| Design And Test Of Hardware Security Primitives |
| Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption | | |
| Florian Krieger, Florian Hirner, Ahmet Can Mert and Sujoy Sinha Roy |
| ESC-NTT: An Elastic, Seamless and Compact Architecture for Multi-Parameter NTT Acceleration | | |
| Zhenyu Guan, Yongqing Zhu, Yicheng Huang, Luchang Lei, Xueyan Wang, Hongyang Jia, Yi Chen, Bo Zhang, Jin Dong and Song Bian |
| SpecScope: Automating Discovery of Exploitable Spectre Gadgets on Black-box Microarchitectures | | |
| Najmeh Nazari, Behnam Omidi, Chongzhou Fang, Hosein Mohammadi Makrani, Setareh Rafatirad, Avesta Sasan, Houman Homayoun and Khaled N. Khasawneh |
| CycPUF: Cyclic Physical Unclonable Function | | |
| Michael Dominguez and Amin Rezaei |
| Modeling Attack Tests and Security Enhancement of the Sub-threshold Voltage Divider Array PUF | | |
| Shengjie Zhou, Yongliang Chen, Xiaole Cui and yun Liu |
| Enhancing Side-Channel Attacks through X-Ray-Induced Leakage Amplification | | |
| Nasr-eddine Ouldei Tebina, Luc Salvo, Laurent Maingault, Nacer-Eddine Zergainoh, Guillaume Hubert and Paolo Maistri |
| PhotonNTT: Energy-efficient Parallel Photonic Number Theoretic Transform Accelerator | | |
| Xianbin LI, Jiaqi Liu, Yuying ZHANG, Yinyi LIU, Jiaxu ZHANG, Chengeng Li, Shixi Chen, Yuxiang Fu, Fengshi Tian, Wei ZHANG and Jiang Xu |
| MABFuzz: Multi-Armed Bandit Algorithms for Fuzzing Processors | | |
| Vasudev Gohil, Rahul Kande, Chen Chen, Jeyavijayan Rajendran and Ahmad-Reza Sadeghi |
| Parasitic Circus: On the Feasibility of Golden-Free PCB Verification | | |
| Maryam Saadat Safa, Patrick Schaumont and Shahin Tajik |
| Late Breaking Results: Breakthrough Architecture with innovative technologies, Design & Test methodologies |
| Late Breaking Results: Single Flux Quantum based Brownian Circuits for Ultra-Low-Power Computing | | |
| Satoshi Kawakami, Yusuke Ohtsubo, Koji Inoue and Masamitsu Tanaka |
| A Scalable Low-Latency FPGA Architecture for Spin Qubit Control through Direct Digital Synthesis | | |
| Mathieu TOUBEIX, Eric Guthmuller, Adrian Evans and Tristan Meunier |
| MNT Bench: Benchmarking Software and Layout Libraries for Field-coupled Nanocomputing | | |
| Simon Hofmann, Marcel Walter and Robert Wille |
| Hidden Cost of Circuit Design with RFETs | | |
| Sajjad Parvin, Chandan Jha, Frank Sill Torres and Rolf Drechsler |
| Optimizing Offload Performance in Heterogeneous MPSoCs | | |
| Luca Colagrande and Luca Benini |
| Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache | | |
| Davy Million, Noelia Oliete-Escuín and César Fuguet |
| LLM-guided Formal Verification Coupled with Mutation Testing | | |
| Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha and Rolf Drechsler |
| Scan-chain Optimization with Constrained Single Linkage Clustering and Geometry-based Cluster Balancing | | |
| Gireesh kumar K M, George Antony, Naiju Karim Abdul and Rahul Rao |
| ObfusGate: Representation Learning-Based Gatekeeper for Hardware-Level Obfuscated Malware Detection | | |
| Zhangying He, Chelsea William Fernandes and Hossein Sayadi |
| Multi-Partner Projects |
| AMBEATion: Analog Mixed-Signal Back-End Design Automation with Machine Learning and Artificial Intelligence Techniques | | |
| Giulia Elena Aliffi, Joao Baixinho, Dalibor Barri, Francesco Daghero, Nicola Di Carolo, Gabriele Faraone, Michelangelo Grosso, Daniele Jahier Pagliari, Jiri Jakovenko, Vladimír Janíček, Dario Licastro, Vazgen Melikyan, Matteo Risso, Vittorio Romano, Eugenio Serianni, Martin Štastný, Patrik Vacula, Giorgia Vitanza and Chen Xie |
| Design Automation for Cyber-Physical Production Systems: Lessons Learned from the DeFacto Project | | |
| Michele Lora, Sebastiano Gaiardelli, Chanwook Oh, Stefano Spellini, Pierluigi Nuzzo and Franco Fummi |
| Formal Methods for High Integrity GPU Software Development and Verification | | |
| Dimitris Aspetakis, Leonidas Kosmidis, Jose Ruiz and Gabor Marosy |
| The METASAT Model-Based Engineering Workflow and Digital Twin Concept | | |
| Alejandro J. Calderon, Irune Yarza, Stefano Sinisi, Lorenzo Lazzara, Valerio Di Valerio, Giulia Stazi, Leonidas Kosmidis, Matina Maria Trompouki, Alessandro Ulisse, Aitor Amonarriz and Peio Onaindia |
| An AI-Enabled Framework for Smart Semiconductor Manufacturing | | |
| Khaled Sidahmed Sidahmed Alamin, Davide Appello, Alessandro Beghi, Nicola Dall'Ora, Fabio Depaoli, Santa Di Cataldo, Franco Fummi, Sebastiano Gaiardelli, Michele Lora, Enrico Macii, Alessio Mascolini, Daniele Pagano, Francesco Ponzio, Gian Antonio Susto and Sara Vinco |
| Design Automation for Quantum Computing: Intermediate Stage Report of the ERC Consolidator Grant "DAQC" | | |
| Robert Wille |
| Focus Session: Smoothing Disruption Across The Stack: Tales Of Memory, Heterogeneity, And Compilers |
| Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, and Compilers | | |
| Julien Ryckaert, Michael Niemier, Zephan Enciso, Mohammad Mehdi Sharifi, X. Sharon Hu, Ian O'Connor, Alexander Graening, Ravit Sharma, Puneet Gupta, Jeronimo Castrillon, Joao Paulo De Lima, Asif Ali Khan, Hamid Farzaneh, Nashrah Afroze and Asif Khan |
| Advanced Formal Methods And Verification |
| Deductive Formal Verification of Synthesizable, Transaction-level Hardware Designs Using Coq | | |
| Tobias Strauch |
| Formal Verification of Booth Radix-8 and Radix-16 Multipliers | | |
| Mertcan Temel |
| PURSE: Property Ordering Using Runtime Statistics for Efficient Multi-Property Verification | | |
| Sourav Das, Aritra Hazra, Pallab Dasgupta, Sudipta Kundu and Himanshu Jain |
| Parallel Grobner Basis Rewriting and Memory Optimization for Efficient Multiplier Verification | | |
| Hongduo Liu, Peiyu Liao, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho and Bei Yu |
| Formal Verification of Secure Boot Process | | |
| sriram vasudevan, PRASANNA RAVI, Arpan Jati, Shivam Bhasin and Anupam Chattopadhyay |
| Complete and Efficient Verification for a RISC-V Processor using Formal Verification | | |
| Lennart Weingarten, Kamalika Datta, Abhoy Kole and Rolf Drechsler |
| A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving | | |
| Oussama Oulkaid, Bruno Ferres, Matthieu Moy, Pascal Raymond, Mehdi Khosravian, Ludovic Henrio and Gabriel Radanne |
| LLM-based Processor Verification: A Case Study for Neuromorphic Processor | | |
| Chao Xiao, Yifei Deng, Zhijie Yang, Renzhi Chen, Hong Wang, Jingyue Zhao, Huadong Dai, Lei Wang, Yuhua Tang and Weixia Xu |
| Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs | | |
| Khalil Esper, Stefan Wildermann and Jürgen Teich |
| AsymSAT: Accelerating SAT Solving with Asymmetric Graph-based Model Prediction | | |
| Zhiyuan Yan, Min Li, Zhengyuan Shi, Wenjie Zhang, Yingcong Chen and Hongce Zhang |
| A Hybrid Approach to Reverse Engineering on Combinational Circuits | | |
| Wuqian Tang, Yi-Ting Li, Kai-Po Hsu, Kuan-Ling Chou, You-Cheng Lin, Chia-Feng Chien, Tzu-Li Hsu, Yung-Chih Chen, Ting-Chi Wang, Shih-Chieh Chang, TingTing Hwang and Chun-Yao Wang |
| Physical Analysis And Design |
| CTRL-B: Back-End-Of-Line Configuration Pathfinding using Cross-Technology Transferable Reinforcement Learning | | |
| Sung-Yun Lee, Kyungjun Min and Seokhyeong Kang |
| A Deep-learning-based Statistical Timing Prediction Method for Sub-16nm Technologies | | |
| Jiajie Xu, Leilei Jin, Wenjie Fu, Hao Yan and Longxing Shi |
| Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes | | |
| Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi and Taewhan Kim |
| BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost | | |
| Chanhee Jeon, Doyeon Won, Jaewan Yang, Kyu-Myung Choi and Taewhan Kim |
| Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner | | |
| Bo Yang, Qi Xu, Hao Geng, Song Chen and Yi Kang |
| Circuits Physics Constrained Predictor of Static IR Drop with Limited Data | | |
| Yuan Meng, Ruiyu Lyv, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou and Xuan Zeng |
| Reinforcement Learning-Based Optimization of Back-side Power Delivery Networks in VLSI Design for IR-drop Reduction | | |
| Seungmin Woo, Hyunsoo Lee, Yunjeong Shin, MinSeok Han, Yunjeong Go, Jongbeom Kim, Hyundong Lee, Hyunwoo Kim and Taigon Song |
| Learning Circuit Placement Techniques through Reinforcement Learning with Adaptive Rewards | | |
| Luke Vassallo and Josef Bajada |
| Training Better CNN Models for 3-D Capacitance Extraction with Neural Architecture Search | | |
| Haoyuan Li, Dingcheng Yang and Wenjian Yu |
| RLPlanner: Reinforcement Learning based Floorplanning for Chiplets with Fast Thermal Analysis | | |
| Yuanyuan Duan, Xingchen Liu, Zhiping Yu, Hanming Wu, Leilai Shao and Xiaolei Zhu |
| Learning to Floorplan like Human Experts via Reinforcement Learning | | |
| Binjie Yan, lin xu, Zefang Yu, Mingye Xie, Wei Ran, Jingsheng Gao, Yuzhuo Fu and Ting Liu |
| Efficient Computing Paradigms For Specific Applications |
| CPF: A Cross-Layer Prefetching Framework for High-Density Flash-based Storage | | |
| Longfei Luo, Han Wang, Yina Lv, Dingcui Yu and Liang Shi |
| A Read Latency Variation Aware Independent Read Scheme for QLC SSDs | | |
| Dong Huang, Dan Feng, Qiankun Liu, Bo Ding, Xueliang Wei, Wei Zhao and Wei Tong |
| Adaptive DRAM Cache Division for Computational Solid-state Drives | | |
| Shuaiwen Yu, zhibing sha, Chengyong Tang, Zhigang Cai, Peng Tang, Min Huang, Jun Li and Jianwei Liao |
| LoADM: Load-aware Directory Migration Policy in Distributed File Systems | | |
| Yuanzhang Wang, Peng Zhang, Fengkui Yang, Ke Zhou and Chunhua Li |
| Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process | | |
| Yuta Shintani, Michiko Inoue and Michihiro Shintani |
| DropHD: Technology/Algorithm Co-design for Reliable Energy-efficient NVM-based Hyperdimensional Computing under Voltage Scaling | | |
| Paul Genssler, Mahta Mayahinia, Simon Thomann, Mehdi Tahoori and Hussam Amrouch |
| An Autonomic Resource Allocating SSD | | |
| Dongjoon Lee, Jongin Choe, Chanyoung Park, Kyungtae Kang, Mahmut Kandemir and Wonil Choi |
| Sparrow: Flexible Memory Deduplication in Android Systems with Similar-Page Awareness | | |
| Guangyu Wei, Changlong Li, Rui Xu, Qingfeng Zhuge and Edwin H.-M. Sha |
| Intelligent Hybrid Memory Scheduling Based on Page Pattern Recognition | | |
| Yanjie Zhen, Weining Chen, Wei Gao, Ju Ren, Kang Chen and Yu Chen |
| Extending SSD Lifetime via Balancing Layer Endurance in 3D NAND Flash Memory | | |
| Siyi Huang, Yajuan Du, Yi Fan and Cheng Ji |
| Special Day on Responsible and Robust AI Lunchtime Keynote |
| Responsible Artificial Intelligence Systems: From trustworthiness to governance | | |
| Francisco Herrera |
| Focus Session: Towards Large Scale Quantum Computing Design: The Quest From Automatic Methods And Tools To Integrated EDA Frameworks |
| From Designing Quantum Processors to Large-Scale Quantum Computing Systems | | |
| Carmen G. Almudever, Robert Wille, Fabio Sebastiano, Nadia Haider and Eduard Alarcon |
| Logical And Physical Analysis And Design |
| Scalable Logic Rewriting Using Don't Cares | | |
| Alessandro Tempia Calvino and Giovanni De Micheli |
| A Semi-Tensor Product based Circuit Simulation for SAT-sweeping | | |
| Hongyang Pan, Ruibing Zhang, Lunyao Wang, Yinshui Xia, Zhufei Chu, Fan Yang and Xuan Zeng |
| BESWAC: Boosting Exact Synthesis via Wiser SAT Solver Call | | |
| Sunan Zou, Jiaxi Zhang, Bizhao Shi and Guojie Luo |
| CBTune: Contextual Bandit Tuning for Logic Synthesis | | |
| Fangzhou Liu, Zehua Pei, Ziyang Yu, Haisheng Zheng, Zhuolun He, Tinghuan Chen and Bei Yu |
| Fast IR-Drop Prediction of Analog Circuits Using Recurrent Synchronized GCN and Y-Net Model | | |
| Seunggyu Lee, Daijoon Hyun, Younggwang Jung, Gangmin Cho and Youngsoo Shin |
| Standard Cells Do Matter: Uncovering Hidden Connections for High-Quality Macro Placement | | |
| Xiaotian Zhao, Tianju Wang, Run Jiao and Xinfei Guo |
| Electrostatics-Based Analytical Global Placement for Timing Optimization | | |
| Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen and Yao-Wen Chang |
| Improvement of Mixed Track-Height Standard-Cell Placement | | |
| Andrew Kahng, Seokhyeong Kang and Minhyuk Kweon |
| BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation | | |
| Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren and Cunxi Yu |
| An Efficient Logic Operation Scheduler for Minimizing Memory Footprint of In-Memory SIMD Computation | | |
| Xingyue Qian, Zhezhi He and Weikang Qian |
| Test Generation, Test Architectures, Design For Test, And Diagnosis |
| Gradient Boosting-accelerated Evolution for Multiple-Fault Diagnosis | | |
| Hongfei Wang, Chenliang Luo, Deqing Zou, Hai Jin and Wenjie Cai |
| A Novel March Test Algorithm for Testing 8T SRAM-based IMC Architectures | | |
| Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noel and Arnaud Virazel |
| Reliable Interval Prediction of Minimum Operating Voltage Based on On-chip Monitors via Conformalized Quantile Regression | | |
| Yuxuan Yin, Xiaoxiao Wang, Rebecca Chen, Chen He and Peng Li |
| PA-2SBF: Pattern-Adaptive Two-Stage Bloom Filter for Run-time Memory Diagnostic Data Compression in Automotive SoCs | | |
| Sunyoung Park, Hyunji Kim, Hana Kim and Ji-Hoon Kim |
| Device-Aware Diagnosis for Yield Learning in RRAMs | | |
| Hanzhi Xun, Moritz Fieback, Sicong Yuan, Hassan AZIZA, Mottaqiallah Taouil and Said Hamdioui |
| Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories | | |
| Spyridon Spyridonos and Yiorgos Tsiatouhas |
| On Gate Flip Errors in Computing-In-Memory | | |
| Zamshed Iqbal Chowdhury, Husrev Cilasun, Salonik Resch, Masoud Zabihi, Yang Lv, Brandon Zink, Jian-Ping Wang, Sachin S. Sapatnekar and Ulya Karpuzcu |
| Guided Fault Injection Strategy for Rapid Critical Bit Detection in Radiation-Prone SRAM-FPGA | | |
| Trishna Rajkumar and Johnny Öberg |
| In-field Detection of Small Delay Defects and Runtime Degradation using On-Chip Sensors | | |
| Seyedehmaryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis Gnad and Mehdi Tahoori |
| Advances On Edge Machine Learning: From Device To Architecture And Application |
| MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting | | |
| Pierpaolo Mori, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder and Claudio Passerone |
| Resource-efficient Heterogenous Federated Continual Learning on Edge | | |
| Zhao Yang, Shengbing Zhang, Chuxi Li, Haoyang Wang and Meng Zhang |
| FMTT: Fused Multi-head Transformer with Tensor-compression for 3D Point Clouds Detection on Edge Devices | | |
| Zikun Wei, Tingting Wang, Chenchen Ding, Bohan Wang, Hantao Huang and Hao Yu |
| XiNet-pose: Extremely lightweight pose detection for microcontrollers | | |
| Alberto Ancilotto, Francesco Paissan and Elisabetta Farella |
| Value-Driven Mixed-Precision Quantization for Patch-Based Inference on Microcontrollers | | |
| Wei Tao, Shenglin He, Kai Lu, Xiaoyang Qu, Guokuan Li, Jiguang Wan, Jianzong Wang and Jing Xiao |
| Tiny-VBF: Resource-Efficient Vision Transformer based Lightweight Beamformer for Ultrasound Single-Angle Plane Wave Imaging | | |
| ABDUL RAHOOF, Vivek Chaturvedi, Mahesh Raveendranatha Panicker and Muhammad Shafique |
| Decentralized Federated Learning in Partially Connected Networks with Non-IID Data | | |
| Xiaojun Cai, Nanxiang Yu, Mengying Zhao, Mei Cao, Tingting Zhang and Jianbo Lu |
| CRISP: Hybrid Structured Sparsity for Class-aware Model Pruning | | |
| Shivam Aggarwal, Kuluhan Binici and Tulika Mitra |
| Work In Progress: Linear Transformers for TinyML | | |
| Moritz Scherer, Cristian Cioflan, Michele Magno and Luca Benini |
| Deep Quasi-Periodic Priors: Signal Separation in Wearable Systems with Limited Data | | |
| Mahya Saffarpour, Kourosh Vali, Weitai Qian, Begum Kasap, Diana L. Farmer, Aijun Wang and Soheil Ghiasi |
| Multi-Partner Projects |
| KIHT: Kaligo-based Intelligent Handwriting Teacher | | |
| Tanja Harbaum, Alexey Serdyuk, Fabian Kreß, Tim Hamann, Jens Barth, Peter Kämpf, Florent Imbert, Yann Soullard, Romain Tavenard, Eric Anquetil and Jessica Delahaie |
| UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents | | |
| Matthias Stammler, Julian Lorenz, Eric Sax, Juergen Becker, Matthias Hamann, Patrick Bidinger, Andreas Dewald, Paraskevi Georgouti, Alexios Camarinopoulos, Günter Becker, Klaus Finsterbusch, Maximilian Kirschner, Laurenz Adolph, Carl Philipp Hohl, Maria Rill, Daniel Vonderau and Victor Pazmino |
| XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems | | |
| Tobias Dörr, Florian Schade, Juergen Becker, Georgios Keramidas, Nikos Petrellis, Vasilios Kelefouras, Michail Mavropoulos, Konstantinos Antonopoulos, Christos P. Antonopoulos, Nikolaos Voros, Alexander Ahlbrecht, Wanja Zaeske, Vincent Janson, Phillip Nöldeke, Umut Durak, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Clemens Reichmann, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Wolfgang Gabler, Katrin Weiden, Xavier Anzuela Recasens, Sakir Sezer, Fahad Siddiqui, Rafiullah Khan, Kieran McLaughlin, Sena Yengec Tasdemir, Balmukund Sonigara, Henry Hui, Esther Soriano Viguer, Aridane Alvarez Suarez, Vicente Nicolau Gallego, Manuel Muñoz Alcobendas and Miguel Masmano Tello |
| Auto-tuning Multi-GPU High-Fidelity Numerical Simulations for Urban Air Mobility | | |
| Konstantina Koliogeorgi, Georgios Anagnostopoulos, Gerardo Zampino, Marcial Sanchis Agudo, Ricardo Vinuesa and Sotirios Xydis |
| A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach | | |
| Christian Pilato, Subhadeep Banik, Jakub Beranek, Fabien Brocheton, Jeronimo Castrillon, Riccardo Cevasco, Radim Cmar, Serena Curzel, Fabrizio Ferrandi, Karl Friebel, Antonella Galizia, Matteo Grasso, Paulo Guimaraes da Silva, Jan Martinovic, Gianluca Palermo, Michele Paolino, Andrea Parodi, Antonio Parodi, Fabio Pintus, Raphael Polig, David Poulet, Francesco Regazzoni, Burkhard Ringlein, Roberto Rocco, Katerina Slaninova, Tom Slooff, Stephanie Soldavini, Felix Suchert, Mattia Tibaldi, Beat Weiss and Christoph Hagleitner |
| Security layers and related services within the Horizon Europe NEUROPULS project | | |
| Fabio Pavanello, Cédric Marchand, Xavier Letartre, Paul Jimenez, Ricardo Chaves, Niccolò Marastoni, Alberto Lovato, Mariano Ceccato, George Papadimitriou, Vasileios Karakostas, Dimitris Gizopoulos, Roberta Bardini, Tzamn Melendez Carmona, Stefano Di Carlo, Alessandro Savino, Laurence Lerch, Ulrich Ruhrmair, Sergio Vinagrero Gutiérrez, Giorgio Di Natale and Elena Ioana Vatajelu |
| SECURED for Health: Scaling up privacy to enable the integration of the European health data space | | |
| Francesco Regazzoni, Paolo Palmieri, George Tasopoulos, Marco Brohet, Kyrian Maat, Zoltan Mann, Kostas Papagiannopoulos, Sotirios Ioannidis, Kalliopi Mastoraki, Andrés G. Castillo Sanz, Joppe W. Bos, Gareth T. Davies, SeoJeong Moon, Alice Héliou, Vincent Thouvenot, Katarzyna Kapusta, Pierre-Elisée Flory, Muhammad Ali Siddiqi, Christos Strydis, Stefanos Florescu, Pieter Kruizinga, Daniela Spajic, Maja Nisevic, Alberto Gutierrez-Torre, Josep Berral, Luca Pulina, Francesca Palumbo, Albert Zoltan Aszalos, Peter Pollner, Vassilis Paliuras, Alexander El-Kady, Christos Tselios:, Konstantina Karagianni, Gergely Acs, Balázs Pejó, Christos Avgerinos, Nikolaos Bakalos, Juan Carlos Perez Baun and Apostolos Fournaris |
| Focus Session: Panel On Resilience Of Deep Learning Applications: Where We Are And Where We Want To Go |
| Panel on resilience of deep learning applications: where we are and where we want to go | | |
| Cristiana Bolchini and Alberto Bosio |
| Reconfigurable Systems |
| AutoWS: Automate Weights Streaming in Layer-wise Pipelined DNN Accelerators | | |
| Zhewen Yu and Christos Bouganis |
| FlexForge: Efficient Reconfigurable Cloud Acceleration via Peripheral Resource Disaggregation | | |
| Se-Min Lim and Sang-Woo Jun |
| WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP | | |
| Tuo Dai, Bizhao Shi and Guojie Luo |
| Optimizing Imperfectly-Nested Loop Mapping on CGRAs via Polyhedral-Guided Flattening | | |
| Xingyu Mo and Dajiang Liu |
| An Efficient Hypergraph Partitioner under Inter-Block Interconnection Constraints | | |
| Benzheng Li, Hailong You, Shunyang Bi and Yuming Zhang |
| REDCAP: Reconfigurable RFET-based Circuits Against Power Side-Channel Attacks | | |
| Nima Kavand, Armin Darjani, Giulio Galderisi, Jens Trommer, Thomas Mikolajick and Akash Kumar |
| Reconfigurable Frequency Multipliers Based on Complementary Ferroelectric Transistors | | |
| Haotian Xu, Jianyi Yang, Cheng Zhuo, Thomas Kampfe, Kai Ni and Xunzhao Yin |
| FeReX: A Reconfigurable Design of Multi-bit Ferroelectric Compute-in-Memory for Nearest Neighbor Search | | |
| Zhicheng XU, Che-Kai Liu, Chao Li, Ruibin Mao, Jianyi Yang, Thomas K ̈ampfe, Mohsen Imani, Can Li, Cheng Zhuo and Xunzhao Yin |
| A Framework for Designing Gaussian Belief Propagation Accelerators for use in SLAM Problems | | |
| Omar Sharif and Christos Bouganis |
| Power-Efficient And Sustainable Computing |
| MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication | | |
| Matteo Perotti, Yichao Zhang, Matheus Cavalcante, Enis Mustafa and Luca Benini |
| DIAC: Design Exploration of Intermittent-Aware Computing Realizing Batteryless Systems | | |
| Sepehr Tabrizchi, Shaahin Angizi and Arman Roohi |
| A Multi-bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application | | |
| Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou and Tian-Sheuan Chang |
| Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent | | |
| Sosei Ikeda, Hiromitsu Awano and Takashi Sato |
| On-sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design | | |
| Giorgos Armeniakos, Paula Lozano Duarte, Priyanjana Pal, Georgios Zervakis, Mehdi Tahoori and Dimitrios Soudris |
| H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations | | |
| Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, Hanchen Yang, Samuel Spetalnick, Tushar Krishna and Arijit Raychowdhury |
| A Hardware Accelerated Autoencoder for RF Communication using Short-Time-Fourier-Transform Assisted Convolutional Neural Network | | |
| Jongseok Woo and Saibal Mukhopadhyay |
| Model-Driven Feature Engineering for Data-Driven Battery SOH Model | | |
| Khaled Sidahmed Sidahmed Alamin, Daniele Jahier Pagliari, Yukai Chen, Enrico Macii, Sara Vinco and Massimo Poncino |
| Search-in-Memory (SiM): Conducting Data-Bound Computations on Flash Memory Chip for Enhanced Efficiency | | |
| Yun-Chih Chen, Yuan-Hao Chang and Tei-Wei Kuo |
| High-Performance Feature Extraction for GPU-accelerated ORB-SLAMx | | |
| Filippo Muzzini, Nicola Capodieci, Roberto Cavicchioli and Benjamin Rouxel |
| Design And Test For Analog And Mixed-Signal Circuits And Systems, And Mems |
| CRONuS: Circuit Rapid Optimization with Neural Simulator | | |
| Youngmin Oh, Doyun Kim, Yoon Hyeok Lee and Bosun Hwang |
| Self-Learning and Transfer across Topologies of Constraints for Analog / Mixed-Signal Circuit Layout Synthesis | | |
| Kaichang Chen and Georges Gielen |
| X-PIM: Fast Modeling and Validation Framework for Mixed-Signal Processing-in-Memory Using Compressed Equivalent Model in SystemVerilog | | |
| Ingu Jeong and Jun-Eun Park |
| tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling | | |
| Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui and Xuan Zeng |
| Adaptive ODE Solvers for Timed Data Flow Models in SystemC-AMS | | |
| Alexandra Kuester, Rainer Dorsch and Christian Haubelt |
| Analog Transistor Placement Optimization Considering Non-Linear Spatial Variation | | |
| Supriyo Maji, Sungyoung Lee and David Pan |
| A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing | | |
| Souradip Poddar, Ahmet Budak, Linran Zhao, Chen-Hao Hsu, Supriyo Maji, Keren Zhu, Yaoyao Jia and David Z. Pan |
| SAGERoute2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios | | |
| Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang and Ru Huang |
| Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation | | |
| Ho-Jin Lee, Kyeong-Jun Lee, Youngchang Choi, Kyongsu Lee, Seokhyeong Kang and Jae-Yoon Sim |
| A Novel Multi-objective Optimization Framework for Analog Circuit Customization | | |
| Mutian Zhu, Qiaochu Zhang, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen, Tony Levi and Sandeep Gupta |
| Late Breaking Results: Innovative AI architecture, circuit and methodology ; Embedded Applications |
| Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine | | |
| Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar and Maya Gokhale |
| Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks | | |
| Ilkin Aliyev and Tosiron Adegbija |
| ClassONN: Classification with Oscillatory Neural Networks using the Kuramoto Model | | |
| Filip Sabo and Aida Todri-Sanial |
| Fluid Dynamic DNNs for Reliable and Adaptive Distributed Inference on Edge Devices | | |
| Lei Xun, Mingyu Hu, Hengrui Zhao, Amit Kumar Singh, Jonathon Hare and Geoff Merrett |
| PIMSIM-NN: An ISA-based Simulation Framework for Processing-in-Memory Accelerators | | |
| Xinyu Wang, Xiaotian Sun, yinhe han and Xiaoming Chen |
| CiMComp: An Energy Efficient Compute-in-Memory based Comparator for Convolutional Neural Networks | | |
| Kavitha Soundra pandiyan, Bhupendra Singh Reniwal and Binsu J Kailath |
| A Sound and Complete Algorithm to Identify Independent Variables in a Reactive System Specification | | |
| Montserrat Hermo, Josu Oca and Alexander Bolotov |
| Late Breaking Results: Iterative Design Automation for Train Control with Hybrid Train Detection | | |
| Stefan Engels and Robert Wille |
| Towards an embedded system for failure diagnosis in drones using AI and SAC-DM on FPGA | | |
| Rafael Batista, Matthias Nickel, Alexander Lehnert, Sergio Pertuz, Marc Reichenbach, Diana Goehringer and Alisson V. Brito |
| Environmental Microchanges in WiFi Sensing | | |
| Cristian Turetta, Philipp H. Kindt, Alejandro Masrur, Samarjit Chakraborty, Graziano Pravadelli and Florenc Demrozi |
